1. Technical Field
The present disclosure relates to nonvolatile memories in integrated circuits on semiconductor chips. More particularly, the present disclosure relates to memories comprising memory cells with programming and erasure by tunneling, called Uniform Channel Program or UCP. More particularly, the present disclosure relates to UCP memory cells with two transistors, comprising a selection transistor and a charge accumulation transistor, such as a floating gate transistor.
2. Description of the Related Art
FIG. 1 is a schematic cross-sectional view of two memory cells C11, C12 of UCP type, fabricated on a P-type substrate PW. Each memory cell C11, C12 comprises a floating gate transistor FGT11, FGT12 and a selection transistor ST11, ST12. Each floating gate transistor comprises a drain region n1 (D), a source region n2 (S), a floating gate FG, a control gate CG, and a channel region CH1 extending under the floating gate FG between the drain n1 and source n2 regions. Each selection transistor ST11, ST12 comprises a drain region n2 (D) common to the source region n2 of the corresponding floating gate transistor FGT11, FGT12, a source region n3 (S), a gate SG, and a channel region CH2 extending under the gate SG between the drain n2 and source n3 regions. The two transistors ST11, ST12 share the same source region n3.
Regions n1, n2, n3 are generally formed by N doping of the substrate PW. The substrate is generally a P-type well formed in a semiconductor wafer WF. The well PW is isolated from the rest of the wafer WF by an N-doped isolation layer NISO that surrounds the entire well. The gates FG, SG are generally of a first layer of polycrystalline silicon “poly1”, and are formed on the substrate PW by means of oxide layers D1, D2, layer D1 being a tunneling oxide layer whereas layer D2 is a gate oxide layer. The control gate CG is generally of a second layer of polycrystalline silicon “poly2”, and is formed on the floating gate FG over an oxide layer D3.
The two memory cells are covered by a dielectric isolating material D0, which may also be of oxide SiO2. The drain regions n1 of transistors FGT11, FGT12 are coupled to a same bitline BL by means of a contact C1 traversing the isolation D0 to reach an intermediary conductor T1 of a first layer of metal “metal1”, and of a conductive via V1 traversing the isolation D0 to couple the conductor T1 to the bitline BL in a second layer of metal “metal2”. The source region n3 common to the two transistors ST11, ST12 is coupled to a source line SL by means of a contact C2 traversing the isolation D0, the source line SL being for example in the first metal layer.
In relation with FIG. 2, table REF1 in Annex describes the voltages applied to the memory cells C11, C12, FIG. 2 showing their equivalent electrical diagram. In relation with FIG. 3, table RD1 in Annex describes voltages values applied to the memory cells during a read of the memory cell C11. Column “Ref.” describes the reference attributed to each voltage value, and the column “Ex.” describes example voltage values. Reference “GND” is the ground potential, that is, the potential of wafer WF, generally 0V.
Thus, during a read of cell C11, the selection transistor ST12 receives the blocking voltage Voff and is not conducting. A current (represented by an arrow in FIG. 3) flows through the channel region CH1 of the transistor FGT11 and through the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11. The threshold voltage is representative of a programmed or erased state of the transistor, which depends on a quantity of electrical charges stored in its floating gate. This current is sensed by a sense amplifier, not shown in the figure, which supplies a binary data stored by the cell C11.
The selection transistor ST12 being blocked by the voltage Voff, the value of the voltage “no-read” Vnread applied to the floating gate transistor FGT12 is unimportant because this transistor is isolated from the source region n3 by the transistor ST12. In the table RD1, this voltage is chosen to be equal to the biasing voltage VB1 of the substrate PW, here the ground potential GND.
Cells C11, C12 have the advantage of being programmable or erasable by application of a pair of determined voltages to the substrate PW and to the control gate CG of their transistor FGT11, FGT12. This programming or erasing mode is called “programming and erasing by the channel”. To give an idea, table ER1 in Annex discloses voltage values applied to the memory cells during erasure of the cell C11. Table PG1 in Annex discloses voltage values applied to memory cells during programming of the cell C11. Reference “HZ” designates the high impedance state (open circuit).
The transfer of charges from the substrate PW to the floating gate FG (programming) or from the floating gate to the substrate (erasure) is done without using the selection transistor ST11, by applying a high voltage difference (here 15V) allowing this charge transfer. Thus, the steps of programming, erasure, and read are performed with low value voltages by exploiting the potential difference between the substrate and the control gate of floating gate transistors. Thus, the selection transistors ST11, ST12 are not subjected to high voltages, which allows memory cells C11, C12 to be provided that are simple to design and do not occupy a lot of semiconductor surface area.
Despite the advantages offered by such UCP memory cells, it may be desired to provide a means allowing their surface area to be decreased even further, in order to reduce the surface area of a memory array comprising a plurality of such memory cells. It may also be desired to provide a memory structure of small surface area.